1. Field of the Invention
The present invention relates to a PLL (Phase-Locked Loop) circuit and a recorded information playback apparatus using the PLL circuit.
2. Description of Related Art
Recent optical disc technology is directed toward higher-density recording and higher-speed reading, as seen from a shift from DVDs (Digital Versatile Discs) to Blu-ray (registered trademark) discs. As a reading system adapted to such higher-density and higher-speed operation, a PRML (Partial Response Maximum Likelihood) system has been in use.
A read channel block adopting the PRML system operates roughly as follows. The high-frequency component of a signal read by an optical pickup from a disc medium is boosted by an equalizer in accordance with a PR equalizing system, and the analog output from the equalizer is digitized by an analog-to-digital converter (hereinafter denoted as “ADC”) for output to a downstream digital signal processing block. Meanwhile, a PLL circuit is formed of the ADC, a phase error detecting circuit, a charge pump circuit, a loop filter, and a voltage-controlled oscillator (hereinafter denoted as “VCO” in a loop configuration. The PLL uses) a VCO clock as a sampling clock for the ADC.
In this read channel block, the PLL circuit feedback-controls the phase of the VCO clock so that a waveform read from the disc medium can be sampled at correct timings. Such a PLL circuit is generally called a clock data recovery circuit or a data synchronizer circuit in the field of recorded information playback apparatuses, such as disc players and magnetic tape players.
Here, how the phase error detecting circuit of the PLL circuit detects phase error will be described.
The phase error detecting circuit uses digital values resulting from the sampling by the ADC of an analog waveform input from the DC component that has been removed by an upstream high-pass filter and the like. When outputs from the ADC undergo a zero crossing, their values preceding and succeeding the zero crossing are added to calculate a phase error.
Let a case of Blu-ray discs be considered as an example. The Blu-ray standard adopts 17PP modulation as a data recording system. Thus, assuming that a reference clock cycle is 1T, it is configured such that the data width changes within a range of 2T to 8T. For ease of explanation, let a case be considered where a 2T signal is continuously inputted. Note that the continuous 2T signals are assumed to have sine waveforms, and the subsequent discussion will be based on this assumption.
FIG. 7 shows a state in which the sampling clock is in correct phase, i.e., the sampling clock is phase-locked, when a waveform is read according to a PR {1, 2, 1} equalizing system. Note that the data amplitude is supposed to be 20 in this example. As an example of a phase error calculating formula in the PR {1, 2, 1} equalizing system, the following equation (1) is available:(y[n−1]+y[n])*sign(y[n])when sign(y[n−1])≠sign(y[n])  (1)
where y[n] represents an n-th sampled value and sign(y[n]) represents the sign of y[n].
A condition in which the above equation (1) yields “0”, i.e., a condition in which the absolute values of two successive sampled values are equal when a zero crossing occurs between these two sampled values, is deemed as a phase-locked state. A specific circuit example for implementing this calculation is shown in FIG. 6.
In FIG. 6, an output from the ADC is held by a register 101 for a period of 1T for determination by a zero crossing determinator 102, which compares the polarity of a current value y[n] with that of a 1T-earlier value y[n−1], as to whether or not a zero crossing has occurred and also as to whether the zero crossing has occurred at the rising or falling of an input waveform. In this example, it is assumed that an EDET signal is set to “1” when a zero crossing has occurred, a FALL signal is set to “0” when the zero crossing has occurred at the rising of the waveform, and “1” when the zero crossing has occurred at the falling of the waveform.
An adder 103 adds two inputted signals when the EDET signal is “1”. A polarity inverting circuit 104 does not invert the polarity of a sum from the adder 103 when the FALL signal is “0”, but inverts the polarity when the FALL signal is “1” to provide a final phase error detection output.
In an example of FIG. 7 showing the phase-locked state of the sampling clock, “20 (amplitude)÷√{square root over (2)}≈±14” are the sampled values outputted from the ADC, and the phase error detection output, i.e., the phase error, thus equals “0” according to the equation (1).
A status is shown in FIG. 8 in which the phase of the sampling clock lags a little bit behind the phase-locked state shown in FIG. 7. Due to the clock getting out of phase, the absolute values of sampled values are not equal before and after their respective zero crossings. In an example of FIG. 8, y[1]=−12 and y[2]=+16 before and after a zero crossing at the rising of an input waveform. A phase error calculated here equals +4 according to the equation (1). Likewise, e.g., y[3]=+12 and y[4]=−16 before and after a zero crossing at the falling, and thus a phase error calculated here is also +4 according to the equation (1).
Next, a case is shown in FIG. 9 where the phase of the sampling clock lags further behind. In this example, a phase shift is a little less than 0.5T=π[rad]. Since y[1]=−1 and y[2]=+19, a phase error here is calculated as +18. Similarly, since y[3]=+1 and y[4]=−19, a phase error here is also calculated as +18.
When the phase of the sampling clock lags still further behind so that the phase shift amount exceeds π[rad], the polarity of the phase error is inverted. In an example shown in FIG. 10, y[1] already moves to the positive side by the phase shift exceeding π [rad]. Thus, following the rule that a phase error is calculated using sampled values preceding and succeeding a zero crossing, a phase error here is calculated from y[0] and y[1]. Since y[0]=−19 and y[1]=+1, the phase error here is calculated as −18. Likewise, in the case of a zero crossing at the falling, y[2]=+19 and y[3]=−1, and thus a phase error also is calculated as −18.
Thus, when schematically expressed, the phase error detection characteristics of the phase error detecting circuit have the shape shown in FIG. 11, exhibiting a monotonously increasing characteristic that is point-symmetrical with respect to the origin when the phase error stays between −π[rad] and +π[rad], and repeating the same characteristic for every 2π[rad] after the phase error exceeds ±π[rad].
By the way, while the phase error detecting circuit has the above phase error detection characteristics, this phase error detecting circuit addresses a problem that frequency locking cannot be implemented when an initial frequency error is large. This problem will be described below.
Referring now to FIG. 11, let a case be considered where there is only an initial frequency error with no initial phase error (=“0”). Since the initial phase error is “0”, the phase error detection output initially stays at the origin of FIG. 11. However, the presence of the initial frequency error causes the phase error to increase gradually as time passes from the start of a PLL operation. In FIG. 11, the phase error detection output gradually grows outward from the origin.
Here, if the initial frequency error is extremely small and thus the phase error increasing speed is sufficiently low compared with a loop operating band width of the PLL, the frequency error is corrected by the PLL operation before the phase error exceeds ±π[rad] to put the phase error detection output back to the origin of FIG. 11. However, if the initial frequency error is large and thus the phase error increases at a speed faster than the PLL operating band width, the PLL functions to correct the frequency error as long as the phase error is ±π[rad] or less, but upon an excess of ±π[rad], the polarity of the phase error detection output is inverted, causing the PLL to encourage the frequency error. As a result, the phase error also aggravates, and thereafter the same phenomenon is repeated for every ±2nπ (where n is an arbitrary natural number). Because of such a phenomenon, the phase error detection output average equals “0” when observed over a long period of time, thus not allowing the frequency offset to be corrected.
In order to compensate for the extremely weak frequency-locking performance of the phase error detecting circuit, in the read channel block, a frequency synthesizer circuit 300 is additionally provided, as shown in FIG. 12. Utilizing a general feature that the reference frequency of a sampling clock can be obtained from the spinning speed of a disc from which data is currently read, the frequency synthesizer circuit 300 generates frequency information to a data synchronizer circuit 200 that uses the PLL circuit including the above-mentioned phase error detecting circuit.
This frequency synthesizer circuit 300 uses an ordinary PLL circuit that can lock both frequency and phase through edge comparison, and thus operates so as to lock onto a data rate reference frequency clock for data being currently read.
Here, the frequency synthesizer circuit 300 generally uses a voltage-controlled oscillator VCO_synth that is the same as a voltage-controlled oscillator VCO_sync used for the data synchronizer circuit 200. And, by giving oscillating frequency information of the voltage-controlled oscillator VCO_synth to the voltage-controlled oscillator VCO_sync beforehand using, e.g., a bias current or the like, an initial frequency offset in the data synchronizer circuit 200 is suppressed within a small range.
Here, a phase detecting circuit used for the frequency synthesizer circuit 300 will be described briefly.
Usually, this phase detecting circuit has an edge comparison type circuit configuration used for a PLL circuit, such as shown in FIG. 13, in which clock signals are used as its inputs. The phase detecting circuit of this type is often called a phase frequency detector (PFD) because it can lock both phase shift and frequency offset.
The phase detection characteristics of this phase frequency detecting circuit are shown in FIG. 14. As seen from the figure, even if the initial frequency offset is large so as to gradually increase the phase error to go beyond ±2π, the polarity of the PFD output always stays on one side. Since the PFD output average is not “0” as observed over a long period of time, the frequency offset can be corrected later.
However, this phase frequency detecting circuit is only capable of comparing edges between two clock signals, and thus it is not applicable to the read channel block that handles an analog waveform, such as a signal read from a disc, as its input.
Now, let the initial frequency offset in the data synchronizer circuit 200 be discussed. Even if the frequency information is delivered to the voltage-controlled oscillator VCO_sync within the data synchronizer circuit 200 using the frequency synthesizer circuit 300 as mentioned above, due to variations during manufacturing processing, differences in in-chip temperature distribution and the like, the voltage-controlled oscillator VCO_synth within the frequency synthesizer circuit 300 and the voltage-controlled oscillator VCO_sync within the data synchronizer circuit 200 do have oscillating frequencies differing from each other, respectively, i.e., the initial frequency offset is introduced into the data synchronization circuit 200. If this initial frequency offset is large, it is feared, as described earlier, that the phase error detecting circuit of the data synchronizer circuit 200 cannot correct its phase error.
To overcome this situation, measures have been taken to, e.g., lay out both circuits 200 and 300 as close to each other as possible on the chip such that they are less affected by the processing and temperature fluctuations. Also, another solution has been proposed, in which a difference (derivative of a phase error) between the current and the last values that are phase comparison results is added to an original phase error detection output for supply to a PLL loop, whereby a synchronization operation is performed even if a frequency difference for locking is large. See, e.g., Japanese Patent Application Publication No. 11-162122 (Patent Document 1).
As already described, when the initial frequency offset is large, the phase error detection output periodically repeats inversion between the positive and negative polarities as shown in FIG. 11. The derivative of such a periodic function is also a periodic function, and its average is also “0”. Hence, frequency locking cannot be implemented even by simply adding the derivative to the phase error detection output.
By contrast, the related art as claimed in claim 1 of Patent Document 1 utilizes the fact that the absolute value of a derivative increases near a bit slip where the polarity of the derivative becomes opposite to what is desired. Then, an arbitrary threshold is given, and when the derivative exceeds the threshold, that derivative is made invalid, whereby it is prevented to make the average equal to “0”, and at the same time, it is enabled to select only a value having the desired polarity.